Here is a catalogue of predefined implicit rules which are always available unless the makefile explicitly overrides or cancels them. See Canceling Implicit Rules, for information on canceling or overriding an implicit rule. The ‘-r’ or ‘--no-builtin-rules’ option cancels all predefined rules.
This manual only documents the default rules available on POSIX-based
operating systems. Other operating systems, such as VMS, Windows,
OS/2, etc. may have different sets of default rules. To see the full
list of default rules and variables available in your version of GNU
make, run ‘make -p’ in a directory with no makefile.
Not all of these rules will always be defined, even when the ‘-r’
option is not given. Many of the predefined implicit rules are
make as suffix rules, so which ones will be
defined depends on the suffix list (the list of prerequisites of
the special target
.SUFFIXES). The default suffix list is:
.el. All of the implicit rules described below
whose prerequisites have one of these suffixes are actually suffix
rules. If you modify the suffix list, the only predefined suffix
rules in effect will be those named by one or two of the suffixes that
are on the list you specify; rules whose suffixes fail to be on the
list are disabled. See Old-Fashioned Suffix Rules,
for full details on suffix rules.
as. The precise recipe is ‘$(AS) $(ASFLAGS)’.
n.s is made automatically from n.S by
running the C preprocessor,
cpp. The precise recipe is
ld) via the C compiler. The precise recipe used is ‘$(CC) $(LDFLAGS) n.o $(LOADLIBES) $(LDLIBS)’.
This rule does the right thing for a simple program with only one source file. It will also do the right thing if there are multiple object files (presumably coming from various other source files), one of which has a name matching that of the executable file. Thus,
x: y.o z.o
when x.c, y.c and z.c all exist will execute:
cc -c x.c -o x.o cc -c y.c -o y.o cc -c z.c -o z.o cc x.o y.o z.o -o x rm -f x.o rm -f y.o rm -f z.o
In more complicated cases, such as when there is no object file whose name derives from the executable file name, you must write an explicit recipe for linking.
Each kind of file automatically made into ‘.o’ object files will
be automatically linked by using the compiler (‘$(CC)’,
‘$(FC)’ or ‘$(PC)’; the C compiler ‘$(CC)’ is used to
assemble ‘.s’ files) without the ‘-c’ option. This could be
done by using the ‘.o’ object files as intermediates, but it is
faster to do the compiling and linking in one step, so that's how it's
The convention of using the same suffix ‘.l’ for all Lex files
regardless of whether they produce C code or Ratfor code makes it
make to determine automatically which of the two
languages you are using in any particular case. If
called upon to remake an object file from a ‘.l’ file, it must
guess which compiler to use. It will guess the C compiler, because
that is more common. If you are using Ratfor, make sure
knows this by mentioning n.r in the makefile. Or, if you
are using Ratfor exclusively, with no C files, remove ‘.c’ from
the list of implicit rule suffixes with:
.SUFFIXES: .SUFFIXES: .o .r .f .l ...
lint. The precise recipe is ‘$(LINT) $(LINTFLAGS) $(CPPFLAGS) -i’. The same recipe is used on the C code produced from n.y or n.l.
For the benefit of SCCS, a file n is copied from n.sh and made executable (by everyone). This is for shell scripts that are checked into SCCS. Since RCS preserves the execution permission of a file, you do not need to use this feature with RCS.
We recommend that you avoid using of SCCS. RCS is widely held to be superior, and is also free. By choosing free software in place of comparable (or inferior) proprietary software, you support the free software movement.
Usually, you want to change only the variables listed in the table above, which are documented in the following section.
However, the recipes in built-in implicit rules actually use
variables such as
PREPROCESS.S, whose values contain the recipes listed above.
make follows the convention that the rule to compile a
.x source file uses the variable
Similarly, the rule to produce an executable from a .x
LINK.x; and the rule to preprocess a
.x file uses
Every rule that produces an object file uses the variable
make defines this variable either to
contain ‘-o $@’, or to be empty, depending on a compile-time
option. You need the ‘-o’ option to ensure that the output goes
into the right file when the source file is in a different directory,
as when using
VPATH (see Directory Search). However,
compilers on some systems do not accept a ‘-o’ switch for object
files. If you use such a system, and use
compilations will put their output in the wrong place.
A possible workaround for this problem is to give
the value ‘; mv $*.o $@’.