The logic element behaves differently depending on the options

In

The

The

`AND`

`NAND`

`OR`

`NOR`

`XOR`

`INV`

`DELAY`=*x*- Propagation delay. (Seconds) (Default = 1e-9) The propagation delay of a simple gate when simulated in logic mode.

`VMAX`=*x*- Nominal logic 1. (Volts) (Default = 5.) The
nominal value for a logic 1.

`VMIN`=*x*- Nominal logic 0. (Volts) (Default = 0.) The
nominal value for a logic 0.

`UNKNOWN`=*x*- Nominal logic unknown. (Volts) (Default = (vmax+vmin)/2) The output voltage for a logic unknown. In a real circuit, this voltage is unknown, but a simulator needs something, so here it is.

`RISE`=*x*- Rise time. (Seconds) (Default = delay / 2) The
nominal rise time of a logic signal. This will be the rise time when
a logic signal is converted to analog.

`FALL`=*x*- Fall time. (Seconds) (Default = delay / 2) The
nominal fall time of a logic signal. This will be the fall time when a
logic signal is converted to analog.

`RS`=*x*- Series resistance, strong. (Ohms) (Default =
100.) The resistance in series with the output when a logic gate drives
analog circuitry.

`RW`=*x*- Series resistance, weak. (Ohms) (Default = 1e9) The output resistance in a high impedance state.

`THH`=*x*- Threshold high. (Unitless) (Default = .75) The
threshold for the input to cross from transition to high expressed as a
fraction of the difference between high and low values. (Low = 0. High =
1.)

`THL`=*x*- Threshold low. (Unitless) (Default = .25) The threshold for the input to cross from transition to low expressed as a fraction of the difference between high and low values. (Low = 0. High = 1.)

`MR`=*x*- Margin rising. (Unitless) (Default = 5) How much
worse than nominal the analog input rise time can be and still be accepted
as clean enough for logic simulation.

`MF`=*x*- Margin falling. (Unitless) (Default = 5) How much
worse than nominal the analog input fall time can be and still be accepted
as clean enough for logic simulation.

`OVER`=*x*- Overshoot limit. (Unitless) (Default = .1) How much overshoot can a signal have and still be accepted as clean enough for logic simulation, expressed as a fraction of the difference between high and low values. (Low = 0. High = 1.)

`V`-
Output voltage.

`LOGIC`-
A numeric interpretation of the logic value at the node. The value is
displayed encoded in a number of the form
*a*.*bc*where*a*is the logic state: 0 = logic 0, 1 = rising, 2 = falling, 3 = logic 1.*b*is an indication of the quality of the digital signal. 0 is a fully valid logic signal. Nonzero indicates it does not meet the criteria for logic simulation.*c*indicates how the node was calculated: 0 indicates logic simulation. 1 indicates analog simulation of a logic device. 2 indicates analog simulation of analog devices.

`LASTCHANGE`-
The most recent time at which the logic state changed.

`FINALTIME`- The scheduled time a pending change will occur.

You can probe the logic value at any node. See the