ports_def_F1.h Source File

00001 /* m68hc11/ports_def.h -- Definition of 68HC11 ports
00002    Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
00003    Written by Stephane Carrez (stcarrez@worldnet.fr)
00004    Adaptions to the 68HC11F1 target by Ingo Beckmann (ib@nnTec.de)
00005 
00006 This file is part of GDB, GAS, and the GNU binutils.
00007 
00008 GDB, GAS, and the GNU binutils are free software; you can redistribute
00009 them and/or modify them under the terms of the GNU General Public
00010 License as published by the Free Software Foundation; either version
00011 1, or (at your option) any later version.
00012 
00013 GDB, GAS, and the GNU binutils are distributed in the hope that they
00014 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00015 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00016 the GNU General Public License for more details.
00017 
00018 You should have received a copy of the GNU General Public License
00019 along with this file; see the file COPYING.  If not, write to the Free
00020 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
00021 
00022 #ifndef _M68HC11_PORTS_DEF_F1_H
00023 #define _M68HC11_PORTS_DEF_F1_H
00024 
00025 /* 68HC11 register address offsets (range 0..0x5F or 0..95).
00026    The absolute address of the I/O register depends on the setting
00027    of the M6811_INIT register.  At init time, the I/O registers are
00028    mapped at 0x1000.  Address of registers is then:
00029 
00030    0x1000 + M6811_xxx
00031 */
00032 #define M6811_PORTA     0x00    /* Port A register */
00033 #define M6811_DDRA      0x01    /* Data direction register for port A */
00034 #define M6811_PORTG     0x02    /* Port G register */
00035 #define M6811_DDRG      0x03    /* Data direction register for port G */
00036 #define M6811_PORTB     0x04    /* Port B register */
00037 #define M6811_PORTF     0x05    /* Port F register */
00038 #define M6811_PORTC     0x06    /* Port C register */
00039 #define M6811_DDRC      0x07    /* Data direction register for port C */
00040 #define M6811_PORTD     0x08    /* Port D register */
00041 #define M6811_DDRD      0x09    /* Data direction register for port D */
00042 #define M6811_PORTE     0x0A    /* Port E input register */
00043 #define M6811_CFORC     0x0B    /* Compare Force Register */
00044 #define M6811_OC1M      0x0C    /* OC1 Action Mask register */
00045 #define M6811_OC1D      0x0D    /* OC1 Action Data register */
00046 #define M6811_TCTN      0x0E    /* Timer Counter Register */
00047 #define M6811_TCTN_H    0x0E    /* "     "       " High part */
00048 #define M6811_TCTN_L    0x0F    /* "     "       " Low part */
00049 #define M6811_TIC1      0x10    /* Input capture 1 register */
00050 #define M6811_TIC1_H    0x10    /* "     "       " High part */
00051 #define M6811_TIC1_L    0x11    /* "     "       " Low part */
00052 #define M6811_TIC2      0x12    /* Input capture 2 register */
00053 #define M6811_TIC2_H    0x12    /* "     "       " High part */
00054 #define M6811_TIC2_L    0x13    /* "     "       " Low part */
00055 #define M6811_TIC3      0x14    /* Input capture 3 register */
00056 #define M6811_TIC3_H    0x14    /* "     "       " High part */
00057 #define M6811_TIC3_L    0x15    /* "     "       " Low part */
00058 #define M6811_TOC1      0x16    /* Output Compare 1 register */
00059 #define M6811_TOC1_H    0x16    /* "     "       " High part */
00060 #define M6811_TOC1_L    0x17    /* "     "       " Low part */
00061 #define M6811_TOC2      0x18    /* Output Compare 2 register */
00062 #define M6811_TOC2_H    0x18    /* "     "       " High part */
00063 #define M6811_TOC2_L    0x19    /* "     "       " Low part */
00064 #define M6811_TOC3      0x1A    /* Output Compare 3 register */
00065 #define M6811_TOC3_H    0x1A    /* "     "       " High part */
00066 #define M6811_TOC3_L    0x1B    /* "     "       " Low part */
00067 #define M6811_TOC4      0x1C    /* Output Compare 4 register */
00068 #define M6811_TOC4_H    0x1C    /* "     "       " High part */
00069 #define M6811_TOC4_L    0x1D    /* "     "       " Low part */
00070 #define M6811_TOC5      0x1E    /* Output Compare 5 register */
00071 #define M6811_TOC5_H    0x1E    /* "     "       " High part */
00072 #define M6811_TOC5_L    0x1F    /* "     "       " Low part */
00073 #define M6811_TCTL1     0x20    /* Timer Control register 1 */
00074 #define M6811_TCTL2     0x21    /* Timer Control register 2 */
00075 #define M6811_TMSK1     0x22    /* Timer Interrupt Mask Register 1 */
00076 #define M6811_TFLG1     0x23    /* Timer Interrupt Flag Register 1 */
00077 #define M6811_TMSK2     0x24    /* Timer Interrupt Mask Register 2 */
00078 #define M6811_TFLG2     0x25    /* Timer Interrupt Flag Register 2 */
00079 #define M6811_PACTL     0x26    /* Pulse Accumulator Control Register */
00080 #define M6811_PACNT     0x27    /* Pulse Accumulator Count Register */
00081 #define M6811_SPCR      0x28    /* SPI Control register */
00082 #define M6811_SPSR      0x29    /* SPI Status register */
00083 #define M6811_SPDR      0x2A    /* SPI Data register */
00084 #define M6811_BAUD      0x2B    /* SCI Baud register */
00085 #define M6811_SCCR1     0x2C    /* SCI Control register 1 */
00086 #define M6811_SCCR2     0x2D    /* SCI Control register 2 */
00087 #define M6811_SCSR      0x2E    /* SCI Status register */
00088 #define M6811_SCDR      0x2F    /* SCI Data (Read => RDR, Write => TDR) */
00089 #define M6811_ADCTL     0x30    /* A/D Control register */
00090 #define M6811_ADR1      0x31    /* A/D, Analog Result register 1 */
00091 #define M6811_ADR2      0x32    /* A/D, Analog Result register 2 */
00092 #define M6811_ADR3      0x33    /* A/D, Analog Result register 3 */
00093 #define M6811_ADR4      0x34    /* A/D, Analog Result register 4 */
00094 #define M6811_BPROT     0x35    /* Block Protect for Config and EPROM */
00095 #define M6811__RES36    0x36
00096 #define M6811__RES37    0x37
00097 #define M6811_OPT2      0x38    /* System Configuration Options 2 */
00098 #define M6811_OPTION    0x39    /* System Configuration Options */
00099 #define M6811_COPRST    0x3A    /* Arm/Reset COP Timer Circuitry */
00100 #define M6811_PPROG     0x3B    /* EEPROM Programming Control Register */
00101 #define M6811_HPRIO     0x3C    /* Highest priority I-Bit int and misc */
00102 #define M6811_INIT      0x3D    /* Ram and I/O mapping register */
00103 #define M6811_TEST1     0x3E    /* Factory test control register */
00104 #define M6811_CONFIG    0x3F    /* COP, ROM and EEPROM enables */
00105 #define M6811__RES40    0x40
00106 #define M6811__RES41    0x41
00107 #define M6811__RES42    0x42
00108 #define M6811__RES43    0x43
00109 #define M6811__RES44    0x44
00110 #define M6811__RES45    0x45
00111 #define M6811__RES46    0x46
00112 #define M6811__RES47    0x47
00113 #define M6811__RES48    0x48
00114 #define M6811__RES49    0x49
00115 #define M6811__RES4A    0x4A
00116 #define M6811__RES4B    0x4B
00117 #define M6811__RES4C    0x4C
00118 #define M6811__RES4D    0x4D
00119 #define M6811__RES4E    0x4E
00120 #define M6811__RES4F    0x4F
00121 #define M6811__RES50    0x50
00122 #define M6811__RES51    0x51
00123 #define M6811__RES52    0x52
00124 #define M6811__RES53    0x53
00125 #define M6811__RES54    0x54
00126 #define M6811__RES55    0x55
00127 #define M6811__RES56    0x56
00128 #define M6811__RES57    0x57
00129 #define M6811__RES58    0x58
00130 #define M6811__RES59    0x59
00131 #define M6811__RES5A    0x5A
00132 #define M6811__RES5B    0x5B
00133 #define M6811_CSSTRH    0x5C    /* Chip-Select Clock Stretch */
00134 #define M6811_CSCTL     0x5D    /* Chip-Select Control */
00135 #define M6811_CSGADR    0x5E    /* General-Purpose Chip-Select Address Register */
00136 #define M6811_CSGSIZ    0x5F    /* Gerenal-Purpose Chip-Select Size Register */
00137 
00138 /* Flags of the CONFIG register (in EEPROM).  */
00139 #define M6811_EE3       0x80    /* EEPROM Map Position Bits */
00140 #define M6811_EE2       0x40    /* EEPROM Map Position Bits */
00141 #define M6811_EE1       0x20    /* EEPROM Map Position Bits */
00142 #define M6811_EE0       0x10    /* EEPROM Map Position Bits */
00143 #define M6811_NOCOP     0x04    /* COP system disable */
00144 #define M6811_EEON      0x01    /* Enable on-chip eeprom */
00145 
00146 /* Flags of the PPROG register.  */
00147 #define M6811_ODD       0x80    /* Program Odd Rows (TEST) */
00148 #define M6811_EVEN      0x40    /* Program Even Rows (TEST) */ 
00149 #define M6811_BYTE      0x10    /* Byte mode */
00150 #define M6811_ROW       0x08    /* Row mode */
00151 #define M6811_ERASE     0x04    /* Erase mode select (1 = erase, 0 = read) */
00152 #define M6811_EELAT     0x02    /* EEPROM Latch Control */
00153 #define M6811_EEPGM     0x01    /* EEPROM Programming Voltage Enable */
00154 
00155 /* Flags of the BPROT register.  */
00156 #define M6811_PTCON     0x10    /* Protect for CONFIG */
00157 #define M6811_BPRT3     0x08    /* Block Protect Bits for EEPROM $xEE0-$xFFF 288 Bytes */
00158 #define M6811_BPRT2     0x04    /* $xE60-$xEDF 128 Bytes */
00159 #define M6811_BPRT1     0x02    /* $xE20-$xE5F 64 Bytes */
00160 #define M6811_BPRT0     0x01    /* $xE00-$xD9F 32 Bytes */
00161 
00162 /* Flags of the SCCR1 register.  */
00163 #define M6811_R8        0x80    /* Receive Data bit 8 */
00164 #define M6811_T8        0x40    /* Transmit data bit 8 */
00165 #define M6811__SCCR1_5  0x20    /* Unused */
00166 #define M6811_M         0x10    /* SCI Character length */
00167 #define M6811_WAKE      0x08    /* Wake up method select (0=idle, 1=addr mark) */
00168 
00169 /* Flags of the SCCR2 register.  */
00170 #define M6811_TIE       0x80    /* Transmit Interrupt enable */
00171 #define M6811_TCIE      0x40    /* Transmit Complete Interrupt Enable */
00172 #define M6811_RIE       0x20    /* Receive Interrupt Enable */
00173 #define M6811_ILIE      0x10    /* Idle Line Interrupt Enable */
00174 #define M6811_TE        0x08    /* Transmit Enable */
00175 #define M6811_RE        0x04    /* Receive Enable */
00176 #define M6811_RWU       0x02    /* Receiver Wake Up */
00177 #define M6811_SBK       0x01    /* Send Break */
00178 
00179 /* Flags of the SCSR register.  */
00180 #define M6811_TDRE      0x80    /* Transmit Data Register Empty */
00181 #define M6811_TC        0x40    /* Transmit Complete */
00182 #define M6811_RDRF      0x20    /* Receive Data Register Full */
00183 #define M6811_IDLE      0x10    /* Idle Line Detect */
00184 #define M6811_OR        0x08    /* Overrun Error */
00185 #define M6811_NF        0x04    /* Noise Flag */
00186 #define M6811_FE        0x02    /* Framing Error */
00187 #define M6811__SCSR_0   0x01    /* Unused */
00188 
00189 /* Flags of the BAUD register.  */
00190 #define M6811_TCLR      0x80    /* Clear Baud Rate (TEST mode) */
00191 #define M6811__BAUD_6   0x40    /* Not used */
00192 #define M6811_SCP1      0x20    /* SCI Baud rate prescaler select */
00193 #define M6811_SCP0      0x10
00194 #define M6811_RCKB      0x08    /* Baud Rate Clock Check (TEST mode) */
00195 #define M6811_SCR2      0x04    /* SCI Baud rate select */
00196 #define M6811_SCR1      0x02
00197 #define M6811_SCR0      0x01
00198 
00199 #define M6811_BAUD_DIV_1        (0)
00200 #define M6811_BAUD_DIV_3        (M6811_SCP0)
00201 #define M6811_BAUD_DIV_4        (M6811_SCP1)
00202 #define M6811_BAUD_DIV_13       (M6811_SCP1|M6811_SCP0)
00203 
00204 /* Flags of the SPCR register.  */
00205 #define M6811_SPIE      0x80    /* Serial Peripheral Interrupt Enable */
00206 #define M6811_SPE       0x40    /* Serial Peripheral System Enable */
00207 #define M6811_DWOM      0x20    /* Port D Wire-OR mode option */
00208 #define M6811_MSTR      0x10    /* Master Mode Select */
00209 #define M6811_CPOL      0x08    /* Clock Polarity */
00210 #define M6811_CPHA      0x04    /* Clock Phase */
00211 #define M6811_SPR1      0x02    /* SPI Clock Rate Select */
00212 #define M6811_SPR0      0x01
00213 
00214 /* Flags of the SPSR register.  */
00215 #define M6811_SPIF      0x80    /* SPI Transfer Complete flag */
00216 #define M6811_WCOL      0x40    /* Write Collision */
00217 #define M6811_MODF      0x10    /* Mode Fault */
00218 
00219 /* Flags of the ADCTL register.  */
00220 #define M6811_CCF       0x80    /* Conversions Complete Flag */
00221 #define M6811_SCAN      0x20    /* Continuous Scan Control */
00222 #define M6811_MULT      0x10    /* Multiple Channel/Single Channel Control */
00223 #define M6811_CD        0x08    /* Channel Select D */
00224 #define M6811_CC        0x04    /*                C */
00225 #define M6811_CB        0x02    /*                B */
00226 #define M6811_CA        0x01    /*                A */
00227 
00228 /* Flags of the CFORC register.  */
00229 #define M6811_FOC1      0x80    /* Force Output Compare 1 */
00230 #define M6811_FOC2      0x40    /*                      2 */
00231 #define M6811_FOC3      0x20    /*                      3 */
00232 #define M6811_FOC4      0x10    /*                      4 */
00233 #define M6811_FOC5      0x08    /*                      5 */
00234 
00235 /* Flags of the OC1M register.  */
00236 #define M6811_OC1M7     0x80    /* Output Compare 7 */
00237 #define M6811_OC1M6     0x40    /*                6 */
00238 #define M6811_OC1M5     0x20    /*                5 */
00239 #define M6811_OC1M4     0x10    /*                4 */
00240 #define M6811_OC1M3     0x08    /*                3 */
00241 
00242 /* Flags of the OC1D register.  */
00243 #define M6811_OC1D7     0x80
00244 #define M6811_OC1D6     0x40
00245 #define M6811_OC1D5     0x20
00246 #define M6811_OC1D4     0x10
00247 #define M6811_OC1D3     0x08
00248 
00249 /* Flags of the TCTL1 register.  */
00250 #define M6811_OM2       0x80    /* Output Mode 2 */
00251 #define M6811_OL2       0x40    /* Output Level 2 */
00252 #define M6811_OM3       0x20
00253 #define M6811_OL3       0x10
00254 #define M6811_OM4       0x08
00255 #define M6811_OL4       0x04
00256 #define M6811_OM5       0x02
00257 #define M6811_OL5       0x01
00258 
00259 /* Flags of the TCTL2 register.  */
00260 #define M6811_EDG4B     0x80    /* Input Edge Capture Control 4 */
00261 #define M6811_EDG4A     0x40
00262 #define M6811_EDG1B     0x20    /* Input 1 */
00263 #define M6811_EDG1A     0x10
00264 #define M6811_EDG2B     0x08    /* Input 2 */
00265 #define M6811_EDG2A     0x04
00266 #define M6811_EDG3B     0x02    /* Input 3 */
00267 #define M6811_EDG3A     0x01
00268 
00269 /* Flags of the TMSK1 register.  */
00270 #define M6811_OC1I      0x80    /* Output Compare 1 Interrupt */
00271 #define M6811_OC2I      0x40    /*                2           */
00272 #define M6811_OC3I      0x20    /*                3           */
00273 #define M6811_OC4I      0x10    /*                4           */
00274 #define M6811_OC5I      0x08    /*                5           */
00275 #define M6811_IC1I      0x04    /* Input Capture  1 Interrupt */
00276 #define M6811_IC2I      0x02    /*                2           */
00277 #define M6811_IC3I      0x01    /*                3           */
00278 
00279 /* Flags of the TFLG1 register.  */
00280 #define M6811_OC1F      0x80    /* Output Compare 1 Flag */
00281 #define M6811_OC2F      0x40    /*                2      */
00282 #define M6811_OC3F      0x20    /*                3      */
00283 #define M6811_OC4F      0x10    /*                4      */
00284 #define M6811_OC5F      0x08    /*                5      */
00285 #define M6811_IC1F      0x04    /* Input Capture  1 Flag */
00286 #define M6811_IC2F      0x02    /*                2      */
00287 #define M6811_IC3F      0x01    /*                3      */
00288 
00289 /* Flags of Timer Interrupt Mask Register 2 (TMSK2).  */
00290 #define M6811_TOI       0x80    /* Timer Overflow Interrupt Enable */
00291 #define M6811_RTII      0x40    /* RTI Interrupt Enable */
00292 #define M6811_PAOVI     0x20    /* Pulse Accumulator Overflow Interrupt En. */
00293 #define M6811_PAII      0x10    /* Pulse Accumulator Interrupt Enable */
00294 #define M6811_PR1       0x02    /* Timer prescaler */
00295 #define M6811_PR0       0x01    /* Timer prescaler */
00296 #define M6811_TPR_1     0x00    /* " " prescale div 1 */
00297 #define M6811_TPR_4     0x01    /* " " prescale div 4 */
00298 #define M6811_TPR_8     0x02    /* " " prescale div 8 */
00299 #define M6811_TPR_16    0x03    /* " " prescale div 16 */
00300 
00301 /* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2).  */
00302 #define M6811_TOF       0x80    /* Timer overflow bit */
00303 #define M6811_RTIF      0x40    /* Read time interrupt flag */
00304 #define M6811_PAOVF     0x20    /* Pulse accumulator overflow Interrupt flag */
00305 #define M6811_PAIF      0x10    /* Pulse accumulator Input Edge " " " */
00306 
00307 /* Flags of Pulse Accumulator Control Register (PACTL).  */
00308 #define M6811_PAEN      0x40    /* Pulse accumulator system enable */
00309 #define M6811_PAMOD     0x20    /* Pulse accumulator mode */
00310 #define M6811_PEDGE     0x10    /* Pulse accumulator edge control */
00311 #define M6811_I4O5      0x04    /* Configure TI4/O5 */
00312 #define M6811_RTR1      0x02    /* RTI Interrupt rates select */
00313 #define M6811_RTR0      0x01    /* " " " " */
00314 
00315 /* Flags of the Options register.  */
00316 #define M6811_ADPU      0x80    /* A/D Powerup */
00317 #define M6811_CSEL      0x40    /* A/D/EE Charge pump clock source select */
00318 #define M6811_IRQE      0x20    /* IRQ Edge/Level sensitive */
00319 #define M6811_DLY       0x10    /* Stop exit turn on delay */
00320 #define M6811_CME       0x08    /* Clock Monitor enable */
00321 #define M6811_FCME      0x04    /* Force Clock Monitor enable */
00322 #define M6811_CR1       0x02    /* COP timer rate select */
00323 #define M6811_CR0       0x01    /* COP timer rate select */
00324 
00325 /* Flags of the OPT2 register */
00326 #define M6811_GWOM      0x80    /* Port G Wired-Or Mode */
00327 #define M6811_CWOM      0x40    /* Port C Wired-Or Mode */
00328 #define M6811_CLK4X     0x20    /* 4x Clock Output Enable  */
00329 
00330 /* Flags of the HPRIO register.  */
00331 #define M6811_RBOOT     0x80    /* Read Bootstrap ROM */
00332 #define M6811_SMOD      0x40    /* Special Mode */
00333 #define M6811_MDA       0x20    /* Mode Select A */
00334 #define M6811_IRV       0x10    /* Internal Read Visibility */
00335 #define M6811_PSEL3     0x08    /* Priority Select */
00336 #define M6811_PSEL2     0x04
00337 #define M6811_PSEL1     0x02
00338 #define M6811_PSEL0     0x01
00339 
00340 /* Flags for the CSSTRH register */
00341 #define M6811_IO1SA     0x80    /* CSIO 1 Clock Delay */
00342 #define M6811_IO1SB     0x40
00343 #define M6811_IO2SA     0x20    /* CSIO 2 Clock Delay */
00344 #define M6811_IO2SB     0x10
00345 #define M6811_GSTHA     0x08    /* General-Purpose Chip-Select Clock Delay */
00346 #define M6811_GSTHB     0x04    
00347 #define M6811_PSTHA     0x02    /* Program Chip-Select Clock Delay */
00348 #define M6811_PSTHB     0x01
00349 
00350 /* Flags for the CSCTL register */
00351 #define M6811_IO1EN     0x80    /* I/O Chip-Select 1 Bit Enable */
00352 #define M6811_IO1PL     0x40    /* I/O Chip-Select 1 Bit Polarity */
00353 #define M6811_IO2EN     0x20    /* I/O Chip-Select 2 Bit Enable */
00354 #define M6811_IO2PL     0x10    /* I/O Chip-Select 2 Bit Polarity */
00355 #define M6811_GCSPR     0x08    /* General Purpose Chip-Select Priority */
00356 #define M6811_PCSEN     0x04    /* Program Chip-Select Enable */
00357 #define M6811_PSIZA     0x02    /* Program Chip-Select Size */
00358 #define M6811_PSIZB     0x01
00359 
00360 /* Flags for the CSGADR register */
00361 #define M6811_GA15      0x80    /* GA[15:10] - General_purpose Chip-Select Starting Address Bits */
00362 #define M6811_GA14      0x40
00363 #define M6811_GA13      0x20
00364 #define M6811_GA12      0x10
00365 #define M6811_GA11      0x08
00366 #define M6811_GA10      0x04
00367 
00368 /* Flags for the CSGSIZ register */
00369 #define M6811_IO1AV     0x80    /* I/O Chip-Select 1 Address Valid */
00370 #define M6811_IO2AV     0x40    /* I/O Chip-Select 2 Address Valid */
00371 #define M6811_GNPOL     0x10    /* General-Purpose Chip-Select Polarity */
00372 #define M6811_GAVLD     0x08    /* General-Purpose Chip-Select Addres Valid */
00373 #define M6811_GSIZA     0x04    /* General-Purpose Chip-Select Size */
00374 #define M6811_GSIZB     0x02
00375 #define M6811_GSIZC     0x01
00376 
00377 
00378 #define M6811_IO_SIZE  (0x60)
00379 
00380 #endif /* _M68HC11_PORTS_DEF_F1_H */