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2.1.2.1 Instruction structure

MIX instructions are codified as words with the following subfield structure:

Subfield fspec Description
ADDRESS (0:2) The first two bytes plus sign are the address field. Combined with the INDEX field, denotes the memory address to be used by the instruction.
INDEX (3:3) The third byte is the index, normally used for indexing the address1.
MOD (4:4) Byte four is used either as an operation code modifier or as a field specification.
OPCODE (5:5) The last (least significant) byte in the word denotes the operation code.

or, graphically,

      ------------------------------------------------
     |   0   |   1   |   2   |   3   |   4   |   5    |
      ------------------------------------------------
     |        ADDRESS        | INDEX |  MOD  | OPCODE |
      ------------------------------------------------

For a given instruction, ‘M’ stands for the memory address obtained after indexing the ADDRESS subfield (using its INDEX byte), and ‘V’ is the contents of the subfield indicated by MOD of the memory cell with address ‘M’. For instance, suppose that we have the following contents of MIX registers and memory cells:

     [rI2] = + 00 63
     [31] = - 10 11 00 11 22

where ‘[n]’ denotes the contents of the nth memory cell and ‘[rI2]’ the contents of register ‘rI22. Let us consider the binary instruction ‘I = - 00 32 02 11 10. For this instruction we have:

     ADDRESS = - 00 32 = -32
     INDEX = 02 = 2
     MOD = 11 = (1:3)
     OPCODE = 10
     
     M = ADDRESS + [rI2] = -32 + 63 = 31
     V = [M](MOD) = (- 10 11 00 11 22)(1:3) = + 00 00 10 11 00

Note that, when computing ‘V’ using a word and an fspec, we apply a left padding to the bytes selected by ‘MOD’ to obtain a complete word as the result.

In the following subsections, we will assign to each MIX instruction a mnemonic, or symbolic name. For instance, the mnemonic of ‘OPCODE’ 10 is ‘LD2’. Thus we can rewrite the above instruction as

     LD2  -32,2(1:3)

or, for a generic instruction:

     MNEMONIC  ADDRESS,INDEX(MOD)

Some instructions are identified by both the OPCODE and the MOD fields. In these cases, the MOD will not appear in the above symbolic representation. Also when ADDRESS or INDEX are zero, they can be omitted. Finally, MOD defaults to (0:5) (meaning the whole word).


Footnotes

[1] The actual memory address the instruction refers to, is obtained by adding to ADDRESS the value of the ‘rI’ register denoted by INDEX.

[2] In general, ‘[X]’ will denote the contents of entity ‘X’; thus, by definition, ‘V = [M](MOD).