Electric supports multiple design technologies. Each technology is a collection of components and connecting wires. In addition, the technology describes all characteristics of its components and wires including the graphical descriptions, design rules, simulation aspects, etc. A technology is a module that can easily be added to Electric to provide a custom design environment. In addition, a technology editor allows interactive creation and modification. Here are some technologies available in Electric:
The system stores both connectivity and geometry so that analysis and synthesis tools can easily acquire the information they need. For example, the incremental design-rule checker uses connectivity information to avoid complaining about situations that other locality-based checkers would erroneously flag. These are the tools available in Electric:
The incremental design-rule checker watches all changes made to the layout, and displays error messages when violations are detected. It checks for spacing errors, notch errors, and minimum size violations.
A hierarchical design-rule checker does a thorough check of the circuit but takes longer to run.
Interfaces exist to external design-rule checkers, including Caliber and Assura.
The electrical-rule checker has two facilities. One examines all well areas, ensuring proper contacts and spacings. The other checks for antenna rules violations.
Electric has a built-in 12-state switch-level simulator, called ALS. It also supports a built-in version of the IRSIM simulator. These simulators display waveforms in a separate window and let users cross-probe from either the waveform or the circuit window.
Electric is able to produce input decks for a number of popular simulators. Users of Electric must obtain these simulators on their own. Here are some of the simulators currently supported:
The PLA generator works from a library of PLA elements, thus allowing customized arrays.
The ROM generator builds a ROM layout from a personality table.
The Pad Frame generator places pad cells around a chip core and wires them together.
The Fill generators place geometry on relevant layers to ensure proper fill during fabrication.
The maze router runs single wires between points.
The sea-of-gates router runs uses multithreading to run wires faster.
Two routers exist for making sure wires are properly placed. The auto router makes explicit connections whereever geometry abuts or overlaps. The mimic router watches user activity, adding extra wires in situations similar to those that the user runs by hand.
The river router runs multiple parallel wires in a channel between cells.
The network consistency checker uses graph isomorphism to compare a layout with its equivalent schematic. It can also compare two different versions of a layout or two different versions of a schematic.
Logical Effort is a system for marking digital schematic gates with fanout information that will produce optimally fast circuits.
The VHDL system can generate VHDL from a layout, and can compile VHDL to netlists of various formats. These netlists can then be simulated with the built-in simulator, turned into layout with the silicon compiler, or saved to disk for use by other systems.
The Silicon Compiler places and routes standard cells from a structural netlist (which can be obtained from VHDL which can be obtained from a schematic drawing).
The compactor adjusts geometry to its minimal spacing in the X and Y axes.
Electric reads and writes libraries of circuitry in its own format. However, for maximum compatibility with other EDA systems, Electric supports a number of popular interchange and manufacturing formats:
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Updated: 1 Jul 2005 smr