GCC 14 Release Series
Changes, New Features, and Fixes

This page is a "brief" summary of some of the huge number of improvements in GCC 14.

Note: GCC 14 has not been released yet, so this document is a work-in-progress.

Caveats

• C: Support for the GCC extension, a structure containing a C99 flexible array member, or a union containing such a structure, is not the last field of another structure, is deprecated. Refer to Zero Length Arrays. Any code relying on this extension should be modifed to ensure that C99 flexible array members only end up at the ends of structures. Please use the warning option -Wflex-array-member-not-at-end to identify all such cases in the source code and modify them.

General Improvements

• OpenMP
  • The requires directive's unified_address requirement is now fulfilled by both AMD GCN and nvptx devices.
  • OpenMP 5.1: Support was added for collapsing imperfectly nested loops and using present as map-type modifier and in defaultmap.
  • OpenMP 5.2: The OMP_TARGET_OFFLOAD=mandatory handling has been updated for the clarifications and changes of the 5.2 specification. For Fortran, the list of directives permitted in Fortran pure procedures was extended. Additionally, the spec change has been implemented for default implicit mapping of C/C++ pointers pointing to unmapped storage.
  • OpenMP 6.0 preview (TR11): The decl attribute is now supported in C++ 11 attributes.
  • The GNU Offloading and Multi Processing Runtime Library Manual has been updated and extended, improving especially the ICV description, memory allocation, and the description of the environment variables and OpenMP routines. On Linux, the libnuma is now used for allocators requesting the nearest-partition trait as detailed in the manual.
• For offload-device code generated via OpenMP and OpenACC, the math and the Fortran runtime libraries will now automatically be linked, when the user or compiler links them on the host side. Thus, it is no longer required to explicitly pass -lm and/or -lgfortran to the offload-device linker using the -foffload-options= flag.
• New configure options: --enable-host-pie, to build the compiler executables as PIE; and --enable-host-bind-now, to link the compiler executables with -Wl,-z,now in order to enable additional hardening.

New Languages and Language specific improvements

C++

• Several C++26 features have been implemented:
  • P2752R3, Static storage for braced initializers (PR110346)

Runtime Library (libstdc++)

• The libstdc++exp.a library now includes all the Filesystem TS symbols from the libstdc++fs.a library. The experimental symbols for the C++23 std::stacktrace class are also in libstdc++exp.a, replacing the libstdc++_libbacktrace.a library that GCC 13 provides. This means that -lstdc++exp is the only library needed for all experimental libstdc++ features.
• Improved experimental support for C++20, including:
  • std::chrono::parse.
• Improved experimental support for C++23, including:
  • The <stacktrace> header is supported by default.
  • Formatters for std::thread::id and std::stacktrace.
  • Some range adaptors now support move-only types.
• Experimental support for C++26, including:
  • Native handles for filebuf, fstream, etc.
  • std::to_string now uses std::format.
  • Enhanced formatting of pointers with std::format.
  • Testable result types for <charconv> functions.
• Faster numeric conversions using std::to_string and std::to_wstring.
• Updated parallel algorithms that are compatible with oneTBB.
• std::numeric_limits<_Float32> and std::numeric_limits<_Float64> are now defined for all standard modes, not only for C++23.
• Using the std::setfill manipulator with std::istream is deprecated.

New Targets and Target Specific Improvements

IA-32/x86-64

• New ISA extension support for Intel AVX-VNNI-INT16 was added. AVX-VNNI-INT16 intrinsics are available via the -mavxvnniint16 compiler switch.
• New ISA extension support for Intel SHA512 was added. SHA512 intrinsics are available via the -msha512 compiler switch.
• New ISA extension support for Intel SM3 was added. SM3 intrinsics are available via the -msm3 compiler switch.
• New ISA extension support for Intel SM4 was added. SM4 intrinsics are available via the -msm4 compiler switch.
• GCC now supports the Intel CPU named Arrow Lake through -march=arrowlake. Based on Alder Lake, the switch further enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions.
• GCC now supports the Intel CPU named Arrow Lake S through -march=arrowlake-s. Based on Arrow Lake, the switch further enables the AVX-VNNI-INT16, SHA512, SM3 and SM4 ISA extensions.
• GCC now supports the Intel CPU named Lunar Lake through -march=lunarlake. Lunar Lake is based on Arrow Lake S.

Operating Systems

Other significant improvements