E.3 X86-specific Facilities

Facilities specific to X86 that are not specific to a particular operating system are declared in sys/platform/x86.h.

Function: const struct cpuid_feature * __x86_get_cpuid_feature_leaf (unsigned int leaf) ¶

Preliminary: | MT-Safe | AS-Safe | AC-Safe | See POSIX Safety Concepts.

Return a pointer to x86 CPU feature structure used by query macros for x86 CPU feature leaf.

Macro: int HAS_CPU_FEATURE (name) ¶

This macro returns a nonzero value (true) if the processor has the feature name.

Macro: int CPU_FEATURE_USABLE (name) ¶

This macro returns a nonzero value (true) if the processor has the feature name and the feature is supported by the operating system.

The supported processor features are:

• ACPI – Thermal Monitor and Software Controlled Clock Facilities.
• ADX – ADX instruction extensions.
• APIC – APIC On-Chip.
• AES – The AES instruction extensions.
• AESKLE – AES Key Locker instructions are enabled by OS.
• AMX_BF16 – Tile computational operations on bfloat16 numbers.
• AMX_INT8 – Tile computational operations on 8-bit numbers.
• AMX_TILE – Tile architecture.
• ARCH_CAPABILITIES – IA32_ARCH_CAPABILITIES MSR.
• AVX – The AVX instruction extensions.
• AVX2 – The AVX2 instruction extensions.
• AVX_VNNI – The AVX-VNNI instruction extensions.
• AVX512_4FMAPS – The AVX512_4FMAPS instruction extensions.
• AVX512_4VNNIW – The AVX512_4VNNIW instruction extensions.
• AVX512_BF16 – The AVX512_BF16 instruction extensions.
• AVX512_BITALG – The AVX512_BITALG instruction extensions.
• AVX512_FP16 – The AVX512_FP16 instruction extensions.
• AVX512_IFMA – The AVX512_IFMA instruction extensions.
• AVX512_VBMI – The AVX512_VBMI instruction extensions.
• AVX512_VBMI2 – The AVX512_VBMI2 instruction extensions.
• AVX512_VNNI – The AVX512_VNNI instruction extensions.
• AVX512_VP2INTERSECT – The AVX512_VP2INTERSECT instruction extensions.
• AVX512_VPOPCNTDQ – The AVX512_VPOPCNTDQ instruction extensions.
• AVX512BW – The AVX512BW instruction extensions.
• AVX512CD – The AVX512CD instruction extensions.
• AVX512ER – The AVX512ER instruction extensions.
• AVX512DQ – The AVX512DQ instruction extensions.
• AVX512F – The AVX512F instruction extensions.
• AVX512PF – The AVX512PF instruction extensions.
• AVX512VL – The AVX512VL instruction extensions.
• BMI1 – BMI1 instructions.
• BMI2 – BMI2 instructions.
• CLDEMOTE – CLDEMOTE instruction.
• CLFLUSHOPT – CLFLUSHOPT instruction.
• CLFSH – CLFLUSH instruction.
• CLWB – CLWB instruction.
• CMOV – Conditional Move instructions.
• CMPXCHG16B – CMPXCHG16B instruction.
• CNXT_ID – L1 Context ID.
• CORE_CAPABILITIES – IA32_CORE_CAPABILITIES MSR.
• CX8 – CMPXCHG8B instruction.
• DCA – Data prefetch from a memory mapped device.
• DE – Debugging Extensions.
• DEPR_FPU_CS_DS – Deprecates FPU CS and FPU DS values.
• DS – Debug Store.
• DS_CPL – CPL Qualified Debug Store.
• DTES64 – 64-bit DS Area.
• EIST – Enhanced Intel SpeedStep technology.
• ENQCMD – Enqueue Stores instructions.
• ERMS – Enhanced REP MOVSB/STOSB.
• F16C – 16-bit floating-point conversion instructions.
• FMA – FMA extensions using YMM state.
• FMA4 – FMA4 instruction extensions.
• FPU – X87 Floating Point Unit On-Chip.
• FSGSBASE – RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instructions.
• FSRCS – Fast Short REP CMP and SCA.
• FSRM – Fast Short REP MOV.
• FSRS – Fast Short REP STO.
• FXSR – FXSAVE and FXRSTOR instructions.
• FZLRM – Fast Zero-Length REP MOV.
• GFNI – GFNI instruction extensions.
• HLE – HLE instruction extensions.
• HTT – Max APIC IDs reserved field is Valid.
• HRESET – History reset.
• HYBRID – Hybrid processor.
• IBRS_IBPB – Indirect branch restricted speculation (IBRS) and the indirect branch predictor barrier (IBPB).
• IBT – Intel Indirect Branch Tracking instruction extensions.
• INVARIANT_TSC – Invariant TSC.
• INVPCID – INVPCID instruction.
• KL – AES Key Locker instructions.
• LAM – Linear Address Masking.
• L1D_FLUSH – IA32_FLUSH_CMD MSR.
• LAHF64_SAHF64 – LAHF/SAHF available in 64-bit mode.
• LM – Long mode.
• LWP – Lightweight profiling.
• LZCNT – LZCNT instruction.
• MCA – Machine Check Architecture.
• MCE – Machine Check Exception.
• MD_CLEAR – MD_CLEAR.
• MMX – Intel MMX Technology.
• MONITOR – MONITOR/MWAIT instructions.
• MOVBE – MOVBE instruction.
• MOVDIRI – MOVDIRI instruction.
• MOVDIR64B – MOVDIR64B instruction.
• MPX – Intel Memory Protection Extensions.
• MSR – Model Specific Registers RDMSR and WRMSR instructions.
• MTRR – Memory Type Range Registers.
• NX – No-execute page protection.
• OSPKE – OS has set CR4.PKE to enable protection keys.
• OSXSAVE – The OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instructions to access XCR0 and to support processor extended state management using XSAVE/XRSTOR.
• PAE – Physical Address Extension.
• PAGE1GB – 1-GByte page.
• PAT – Page Attribute Table.
• PBE – Pending Break Enable.
• PCID – Process-context identifiers.
• PCLMULQDQ – PCLMULQDQ instruction.
• PCONFIG – PCONFIG instruction.
• PDCM – Perfmon and Debug Capability.
• PGE – Page Global Bit.
• PKS – Protection keys for supervisor-mode pages.
• PKU – Protection keys for user-mode pages.
• POPCNT – POPCNT instruction.
• PREFETCHW – PREFETCHW instruction.
• PREFETCHWT1 – PREFETCHWT1 instruction.
• PSE – Page Size Extension.
• PSE_36 – 36-Bit Page Size Extension.
• PSN – Processor Serial Number.
• RDPID – RDPID instruction.
• RDRAND – RDRAND instruction.
• RDSEED – RDSEED instruction.
• RDT_A – Intel Resource Director Technology (Intel RDT) Allocation capability.
• RDT_M – Intel Resource Director Technology (Intel RDT) Monitoring capability.
• RDTSCP – RDTSCP instruction.
• RTM – RTM instruction extensions.
• SDBG – IA32_DEBUG_INTERFACE MSR for silicon debug.
• SEP – SYSENTER and SYSEXIT instructions.
• SERIALIZE – SERIALIZE instruction.
• SGX – Intel Software Guard Extensions.
• SGX_LC – SGX Launch Configuration.
• SHA – SHA instruction extensions.
• SHSTK – Intel Shadow Stack instruction extensions.
• SMAP – Supervisor-Mode Access Prevention.
• SMEP – Supervisor-Mode Execution Prevention.
• SMX – Safer Mode Extensions.
• SS – Self Snoop.
• SSBD – Speculative Store Bypass Disable (SSBD).
• SSE – Streaming SIMD Extensions.
• SSE2 – Streaming SIMD Extensions 2.
• SSE3 – Streaming SIMD Extensions 3.
• SSE4_1 – Streaming SIMD Extensions 4.1.
• SSE4_2 – Streaming SIMD Extensions 4.2.
• SSE4A – SSE4A instruction extensions.
• SSSE3 – Supplemental Streaming SIMD Extensions 3.
• STIBP – Single thread indirect branch predictors (STIBP).
• SVM – Secure Virtual Machine.
• SYSCALL_SYSRET – SYSCALL/SYSRET instructions.
• TBM – Trailing bit manipulation instructions.
• TM – Thermal Monitor.
• TM2 – Thermal Monitor 2.
• TRACE – Intel Processor Trace.
• TSC – Time Stamp Counter. RDTSC instruction.
• TSC_ADJUST – IA32_TSC_ADJUST MSR.
• TSC_DEADLINE – Local APIC timer supports one-shot operation using a TSC deadline value.
• TSXLDTRK – TSXLDTRK instructions.
• UINTR – User interrupts.
• UMIP – User-mode instruction prevention.
• VAES – VAES instruction extensions.
• VME – Virtual 8086 Mode Enhancements.
• VMX – Virtual Machine Extensions.
• VPCLMULQDQ – VPCLMULQDQ instruction.
• WAITPKG – WAITPKG instruction extensions.
• WBNOINVD – WBINVD/WBNOINVD instructions.
• WIDE_KL – AES wide Key Locker instructions.
• X2APIC – x2APIC.
• XFD – Extended Feature Disable (XFD).
• XGETBV_ECX_1 – XGETBV with ECX = 1.
• XOP – XOP instruction extensions.
• XSAVE – The XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV instructions, and XCR0.
• XSAVEC – XSAVEC instruction.
• XSAVEOPT – XSAVEOPT instruction.
• XSAVES – XSAVES/XRSTORS instructions.
• XTPRUPDCTRL – xTPR Update Control.

You could query if a processor supports AVX with:

#include <sys/platform/x86.h>

int
support_avx (void)
{
  return HAS_CPU_FEATURE (AVX);
}

and if AVX is usable with:

#include <sys/platform/x86.h>

int
usable_avx (void)
{
  return CPU_FEATURE_USABLE (AVX);
}