On Tuesday, October 13, 2020 at 10:41:12 AM UTC-6, Kevin Neilson wrote:> On Monday, October 12, 2020 at 9:18:13 PM UTC-6, Kevin Simonson wrote:=20 > > gnuarm.del...@gmail.com (Rick C.): "In RTL this would be something like=... / Out <=3D '1' when leftOp < rightOp else '0';"=20> >=20 > > I tried:=20 > > // (c) Kevin Simonson 2020=20 > >=20 > > module lessThan=20 > > #( parameter nmBits =3D 1)=20 > > ( output lssThn=20 > > , input [ nmBits-1:0] leftOp=20 > > , input [ nmBits-1:0] rightOp);=20 > > assign lssThn =3D leftOp < rightOp ? 1 : 0;=20 > >=20 > > endmodule=20 > >=20 > > and got the results I was looking for. So there's my low level code tha=t I posted yesterday, and this very high level code that I've posted today;= is there nothing in between? It just bugs me that with the version posted = here I have so little control over how the less than ("<") operator is actu= ally implemented. I think my low level code is pretty much guaranteed to do= a less than comparison on any two operands with an absolute minimum of wor= st case time. Can I say the same for how "leftOp < rightOp" is implemented?= =20> >=20 > > "Is that more clear?" Yes; thanks!=20 > >=20 > > "You might try implementing something like this and compare the result =to your highly specified code in synthesis. So how they both turn out." Ric= h, I'd really like to do that. Unfortunately the tool I'm using to simulate= is Icarus, and when I try to simulate it I get:=20> >=20 > > D:\Hf\Verilog\Unpacked\Src\Common>\Icarus\bin\iverilog -g2009 -o lessTh=an.vvp lessThan.sv=20> > lessThan.sv:81: error: Unable to bind parameter `ndTypes[gnIx]' in `les=sThan.$gen1[1]'=20> > lessThan.sv:81: error: Cannot evaluate genvar case expression: ndTypes[=gnIx]=20> > 2 error(s) during elaboration.=20 > >=20 > > D:\Hf\Verilog\Unpacked\Src\Common>=20 > >=20 > > Any idea why Icarus is giving me these error messages?=20 > >=20 > > By the way, you said, "compare the result to your highly specified code=in synthesis." Can one synthesize with Icarus? If so, how? If not, can you= recommend a tool for synthesis?> First of all, your code needs comments. To you, it might make sense (at l=east at the moment), but you can't expect anybody to be able to help if you= publish a hundred lines of incoherence without even a 1-line comment of wh= at it's supposed to be.=20>=20 > If all you want is a comparator, you don't even need the ?: operator. It'=s just:=20>=20 > wire less_than =3D left_op < right_op;=20 >=20 > I don't even know why you'd want to put this in a separate module; just u=se it where you need it, or in an if-clause:=20>=20 > if (left_op < right_op) do_stuff;=20 >=20 > Sometimes the synthesizer will not do a great job with abstract code. Thi=s is not such a case. You do not need to write low-level code for a subtrac= tor. In an FPGA, for example, the line I wrote above will be synthesized us= ing a built-in carry chain logic. Your code, in which you instantiate primi= tives, will end up with poorer results, because it won't use the fast carry= chain. Some notes:=20>=20 > - Use lots of comments.=20 > - Don't instantiate any primitives unless absolutely necessary for perfor=mance.=20> - Avoid unnecessary hierarchy and "generate" blocks.=20 >=20 > I have not used it much but I recently found a site called "EDA Playgroun=d" in which you can simulate using various simulators and also synthesize u= sing Mentor Questa, a commercial synthesizer. I'm not familiar with Questa,= but here is a link with a simple example. You could set up your own "playg= round" and synthesize. I don't know if you can view the resulting schematic= s, but you can at least get resulting utilization statistics:=20>=20 > https://www.edaplayground.com/x/2BmJSorry; I meant the Mentor *Precision* synthesizer. Questa (n=C3=A9e Models= im) is the simulator.